Clock generator using resistive components to generate sub-gate delays and/or using common-mode voltage based frequency-locked loop circuit for frequency offset reduction
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United States of America Patent
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May 16, 2017
Grant Date -
Apr 27, 2017
app pub date -
Sep 10, 2016
filing date -
Oct 27, 2015
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Abstract
A clock generator has a multi-phase controllable oscillator. The multi-phase controllable oscillator includes oscillator core circuits, and has phase nodes at which clock signals with different phases are generated, respectively. Each oscillator core circuit includes a resistive component and an inverter. The resistive component is coupled between a first phase node and a second phase node of the multi-phase controllable oscillator, wherein clock signals generated at the first phase node and the second phase node have adjacent phases. The resistive components of the oscillator core circuits are cascaded in a ring configuration. The inverter receives an input feedback clock signal from one phase node of the multi-phase controllable oscillator, and generates an output feedback clock signal to the second phase node according to the input feedback clock signal.
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