Computing device and method for determining wiring paths on printed circuit board
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United States of America Patent
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May 23, 2017
Issued Date -
N/A
app pub date -
Jul 6, 2015
filing date -
Jun 1, 2015
priority date (Note) -
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Abstract
A printed circuit board (PCB) layout method executed in a computing device obtains pins of a first electronic component that are connected to a second electronic component or third electronic components included in a T topology circuit. A model of the first electronic component is created according to the obtained pins and is modified to form extended nets of the first electronic component. Pin pairs and match groups are set. Wiring paths of the T topology circuit are determined according to the match groups. The wiring paths are output to an output device.
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