High-voltage field-effect transistor having multiple implanted layers
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United States of America Patent
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May 23, 2017
Grant Date -
Jan 15, 2015
app pub date -
Jul 12, 2013
filing date -
Jul 12, 2013
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Abstract
A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region.
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