Isolated through silicon via and isolated deep silicon via having total or partial isolation
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jun 6, 2017
Issued Date -
N/A
app pub date -
May 1, 2013
filing date -
May 25, 2012
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Disclosed are a structure for improving electrical signal isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench having sidewalls disposed in the semiconductor substrate. An isolation region may be formed along at least an upper portion of the sidewalls of the deep trench, and a metallic filler may be disposed in the deep trench. The isolation region may include a PN junction formed by one or more of ion implantation and annealing, deposition of highly doped polysilicon and out diffusion, and gas phase doping and annealing. In the alternative, the isolation region may be a dielectric isolation region formed by one or more of uniform dielectric deposition, partial dieletric deposition, and dielectric deposition by ionic reaction.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully