Seed layers for metallic interconnects

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United States of America Patent

PATENT NO 9673090
APP PUB NO 20090233440A1
SERIAL NO

12471571

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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One embodiment of the present invention is a method for depositing two or more PVD seed layers for electroplating metallic interconnects over a substrate, the substrate including a patterned insulating layer which includes at least one opening surrounded by a field, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing by a PVD technique, in a PVD chamber, a continuous PVD seed layer over the sidewalls and bottom of the at least one opening, using a first set of deposition parameters; and (b) depositing by a PVD technique, in a PVD chamber, another PVD seed layer over the substrate, using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least one deposition parameter whose value is different in the two sets of deposition parameters, (ii) at least one of the PVD seed layers includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals, (iii) the PVD seed layers have no substantial overhangs sealing or pinching-off the top corners of the at least one opening, (iv) the combined thickness of the seed layers over the field is sufficient to enable uniform electroplating across the substrate, and (v) the combined seed layers inside the at least one opening leave sufficient room for electroplating inside the at least one opening.

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Patent Owner(s)

  • SEED LAYERS TECHNOLOGY LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cohen, Uri Palo Alto, US 56 1231

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