Distributed cache coherent shared memory controller integrated with a protocol offload network interface card
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United States of America Patent
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Jun 20, 2017
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N/A
app pub date -
Aug 7, 2014
filing date -
Aug 7, 2014
priority date (Note) -
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Abstract
Network interface circuitry forms a local node. At least one processor offloads from a host computer at least one stateful communication connection between the host computer and a peer, and also operates a cache coherence protocol to scale coherent memory to multiple nodes. The processor operates the communication protocol processing offload at least in part according to communication connection states maintained in the memory, including accessing each communication connection state in the memory using the access procedure, to access that communication connection state in the memory according to an identifier corresponding to that communication connection state. The processor further operates the cache coherence protocol at least in part according to coherence states maintained in the memory, including accessing each coherence state in the memory using the access procedure, to access that coherence state in the memory according to an identifier corresponding to that coherence state.
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