Code optimization to enable and disable coalescing of memory transactions

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United States of America Patent

PATENT NO 9690556
APP PUB NO 20160283213A1
SERIAL NO

15173758

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A transactional memory system controls the coalescing of outermost memory transactions. The coalescing causing committing of memory store data to memory for a first transaction to be done at transaction execution (TX) end of a second transaction. A processor of the transactional memory system executes a run-time instrumentation program for monitoring and modifying an associated program having a plurality of transactions. Based, at least in part, on an analysis of gathered instrumentation information, the processor dynamically modifies continued execution of the plurality of transactions by adding a coalescing instruction that controls, at least in part, a coalescing of one or more outermost transactions of the plurality of transactions.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Busaba, Fadi Y Poughkeepsie, US 218 1678
Gschwind, Michael Karl Chappaqua, US 345 4144
Michael, Maged M Danbury, US 131 1876
Salapura, Valentina Chappaqua, US 570 7608
Shum, Chung-Lung K Wappingers Falls, US 315 2136

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