Managing cache coherence for memory caches
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United States of America Patent
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Jul 11, 2017
Issued Date -
N/A
app pub date -
Sep 30, 2015
filing date -
Aug 19, 2015
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Abstract
A computer system has a plurality of processors with non-blocking memory caches. A controller sets an upper limit of allowed snoop commands for the computer system. The controller adjusts, using real-time bandwidth data of the computing system, the limit of snoop commands to a new numerical value. The controller detects that the snoop limit is being adjusted between snoop rates more than a threshold number of times. The controller designates an overriding limit of snoop commands in response to detecting the snoop limit being adjusted more than the threshold number of times. The overriding limit of snoop commands is fixed for a period of time. The controller delays snoop commands which exceed the overriding limit of snoop commands during the period of time.
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