Reset current delivery in non-volatile random access memory
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United States of America Patent
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Jul 25, 2017
Grant Date -
Dec 8, 2016
app pub date -
Jun 4, 2015
filing date -
Jun 4, 2015
priority date (Note) -
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Abstract
Embodiments of the present disclosure describe techniques and configurations for providing a reset current to a non-volatile random access memory (NVRAM), such as a phase change memory (PCM) device. In an embodiment, the apparatus may comprise an NVRAM device; a selection mirror circuit coupled with the NVRAM device to apply a selection mirror voltage to the NVRAM device, to select a memory cell of the NVRAM device; and a reset mirror circuit coupled with the NVRAM device to apply a reset mirror voltage to the memory cell of the NVRAM device, subsequent to the application of the selection mirror voltage, to reset the memory cell. The reset mirror voltage may be lower than the selection mirror voltage, to facilitate delivery of a reset current above a current threshold to the memory cell. Other embodiments may be described and/or claimed.
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