Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias

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United States of America Patent

PATENT NO 9716066
APP PUB NO 20160049371A1
SERIAL NO

14779022

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Abstract

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A 3D interconnect structure and method of manufacture are described in which metal redistribution layers (RDLs) are integrated with through-silicon vias (TSVs) and using a “plate through resist” type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and polish stop layer during the process flow.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chang, Hsiao-Kang Hillsboro, US 33 85
Jeong, James Y Beaverton, US 5 53
Kang, Jiho Beaverton, US 6 55
Lee, Kevin J Beaverton, US 73 1110
Muirhead, John Portland, US 2 47
Patel, Nitin M Hillsboro, US 5 134
Puri, Puneesh Aloha, US 2 52
Telang, Adwait Beaverton, US 2 64

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