Using thresholds to gate timing packet generation in a tracing system

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United States of America Patent

PATENT NO 9716646
SERIAL NO

14334071

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Abstract

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In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Kurts, Tsvika Haifa, IL 41 441
Levy, Ofer Atlit, IL 84 370
Malka, Gabi Haifa, IL 12 195
Sperber, Zeev Zichron Yackov, IL 256 1702
Strong, Beeman C Portland, US 24 203

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