Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9720697
APP PUB NO 20130054940A1
SERIAL NO

13608970

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Abstract

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In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Aggarwal, Anil Portland, US 35 736
Bigbee, Bryant Scottsdale, US 28 699
Chinya, Gautham Hillsboro, US 38 569
Grochowski, Ed San Jose, US 14 285
Hammarlund, Per Hillsboro, US 86 1756
Hankins, Richard Andrew San Jose, US 2 110
Held, James Paul Portland, US 7 269
Kaushik, Shivnandan D Portland, US 38 1360
Patel, Baiju V Portland, US 84 1780
Rodgers, Scott Dion Hillsboro, US 49 821
Sethi, Prashant Folsom, US 88 1541
Shen, John San Jose, US 63 1878
Tian, Xinmin Union City, US 50 1078
Wang, Hong Fremont, US 1083 12412
Zou, Xiang Portland, US 104 1793

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