Processing system with interspersed processors with multi-layer interconnection
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United States of America Patent
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Aug 1, 2017
Grant Date -
Nov 17, 2016
app pub date -
Jul 25, 2016
filing date -
Nov 21, 2012
priority date (Note) -
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Abstract
Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.
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