Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof

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United States of America Patent

PATENT NO 9721799
SERIAL NO

14536253

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Abstract

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The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes.

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Patent Owner(s)

  • ADVANCED SEMICONDUCTOR ENGINEERING, INC.

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lee, Chih-Cheng Kaohsiung, TW 100 204
Shih, Yu-Lin Kaohsiung, TW 17 52

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