Land side and die side cavities to reduce package z-height

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United States of America Patent

PATENT NO 9721882
SERIAL NO

15419087

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Importance

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Abstract

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A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die mounted to a die side surface of the package substrate, and the opposing land side surface of the package substrate may be mounted to a printed circuit board (PCB). The capacitor may be mounted within a cavity formed in the die side surface of the package substrate or the land side surface of the package substrate. Mounting a capacitor within a cavity may reduce the form factor of the package. The die may be mounted within a cavity formed in the die side surface of the package substrate. Solder balls connecting the package to the PCB may be mounted within one or more cavities formed in one or both of the package substrate and the PCB.

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Patent Owner(s)

  • INTEL CORPORATION

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gilbert, Scott A Chandler, US 10 43
Hossain, MD Altaf Portland, US 77 139

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