2-D gather instruction and a 2-D cache

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United States of America Patent

PATENT NO 9727476
APP PUB NO 20150178217A1
SERIAL NO

14635403

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Abstract

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A processor may support a two-dimensional (2-D) gather instruction and a 2-D cache. The processor may perform the 2-D gather instruction to access one or more sub-blocks of data from a 2-D image stored in a memory coupled to the processor. The 2-D cache may store the sub-blocks of data in a multiple cache lines. Further, the 2-D cache may support access of more than one cache lines while preserving a 2-D structure of the 2-D image.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ginzburg, Boris Haifa, IL 112 2385
Margulis, Oleg Haifa, IL 21 406

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