Systems and methods for transmitting packets in a scalable memory system protocol
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United States of America Patent
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Aug 15, 2017
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N/A
app pub date -
May 28, 2015
filing date -
Jun 2, 2014
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Abstract
A memory device includes a memory component that store data and a processor. The processor may generate one or more data packets associated with the memory component. Each data packet may include a transaction type field that includes data indicative of a first size of a payload of the respective data packet and a second size of an error control code in the respective data packet. Each packet may also have a payload field that includes the payload and an error control code field that includes the error control code. The processor may transmit the data packets to a requesting component, such that the requesting component identifies the payload field and the error control field of each data packet based on the data of the transaction type field in each data packet.
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