Separate memory address translations for instruction fetches and data accesses
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United States of America Patent
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Aug 15, 2017
Grant Date -
Oct 1, 2015
app pub date -
Mar 31, 2014
filing date -
Mar 31, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
An address translation capability in which a processor obtains an address to be translated, and translates the address from the address to the another address. The translating includes determining an attribute of the address to be translated, and based on the attribute being a first attribute, first information is selected to be used in translating the address. Further, based on the attribute being a second attribute, second information is selected to be used in translating the address. The selected information is used to translate the address to the another address. The another address indicates one memory location based on the selected information being the selected first information, and another memory location based on the selected information being the selected second information.
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