Bond via array for thermal conductivity
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United States of America Patent
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Aug 15, 2017
Grant Date -
Jun 16, 2016
app pub date -
Dec 11, 2014
filing date -
Dec 11, 2014
priority date (Note) -
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Abstract
In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects couple the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical communication therebetween. A via array has proximal ends of wires thereof coupled to the second upper surface for conduction of heat away from the integrated circuit die. A molding material is disposed in the via array with distal ends of the wires of the via array extending at least to a superior surface of the molding material.
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