Semiconductor package
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United States of America Patent
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Aug 15, 2017
Grant Date -
N/A
app pub date -
Nov 22, 2016
filing date -
Aug 10, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The insulating protection layer is disposed on a first active surface of the first chip and includes a concave. Projections of a plurality of first inner pads and a plurality of first outer pads of the first chip projected on the insulating protection layer are located in the concave and out of the concave, respectively. The second chip is flipped on the concave and includes a plurality of second pads. Each of the first inner pads is electrically connected to the corresponding second pad through the corresponding second conductive bump. The underfill is disposed between the concave and the second chip and covers the second conductive bumps.
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