Vector generate mask instruction

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United States of America Patent

PATENT NO 9740482
SERIAL NO

14561815

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Abstract

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A Vector Generate Mask instruction. For each element in the first operand, a bit mask is generated. The mask includes bits set to a selected value starting at a position specified by a first field of the instruction and ending at a position specified by a second field of the instruction.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bradbury, Jonathan D Poughkeepsie, US 270 2078
Enenkel, Robert F Markham, CA 17 161
Schwarz, Eric M Gardiner, US 252 3105
Slegel, Timothy J Staatsburg, US 400 5861

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