Processor directly storing address range of co-processor memory accesses in a transactional memory where co-processor supplements functions of the processor
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United States of America Patent
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Aug 22, 2017
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N/A
app pub date -
Aug 13, 2015
filing date -
Jun 27, 2014
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Abstract
Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by the processor. The processor executes a transactional memory (TM) transaction, including receiving, by the processor, a memory address range of data that a co-processor may access to perform a co-processor operation. The processor saves the memory address range. Based on receiving, by the processor, a cache coherency request that conflicts with the saved address range, the processor aborts the TM transaction.
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