FinFET device with vertical silicide on recessed source/drain epitaxy regions
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United States of America Patent
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Aug 22, 2017
Issued Date -
N/A
app pub date -
Nov 23, 2016
filing date -
Apr 22, 2014
priority date (Note) -
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Abstract
A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.
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