Multi-section garbage collection system including shared performance monitor register
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United States of America Patent
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Aug 29, 2017
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app pub date -
Dec 17, 2015
filing date -
Dec 17, 2015
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Abstract
A system includes memory and a hardware processor. The memory includes a load-monitored region register (LMRR) and a sampled data address register (SDAR). The hardware processor is configured to perform a garbage collection process that reclaims unused objects of the memory. The hardware processor further executes a performance monitoring process that provides information indicating a utilization of an instruction performed by the hardware processor. The SDAR is configured to store first data generated according to the garbage process and second data generated according to the performance monitoring process.
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