Memory rank and ODT configuration in a memory system

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United States of America Patent

PATENT NO 9747230
SERIAL NO

14408955

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Abstract

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A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks. For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

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Patent Owner(s)

  • RAMBUS INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Amirkhany, Amir Sunnyvale, US 102 1053
Han, Minghui San Jose, US 7 60
Kollipara, Ravindranath Palo Alto, US 22 192
Schmitt, Ralf Michael Mountain View, US 2 38

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