Semiconductor package structure including die and substrate electrically connected through conductive segments

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United States of America Patent

PATENT NO 9748196
SERIAL NO

14486755

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Abstract

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The present disclosure relates to a semiconductor package structure, including a die and a package substrate. The die includes a semiconductor substrate, multiple interconnect metal layers, and at least one inter-level dielectric disposed between ones of the interconnect metal layers. Each inter-level dielectric is formed of a low k material. An outermost interconnect metal layer has multiple first conductive segments exposed from a surface of the inter-level dielectric. The package substrate includes a substrate body and multiple second conductive segments exposed from a surface of the substrate body. The second conductive segments are electrically connected to the first conductive segments.

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Patent Owner(s)

  • ADVANCED SEMICONDUCTOR ENGINEERING, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Kuo-Hua Kaohsiung, TW 40 134
Fang, Jen-Kuang Kaohsiung, TW 65 391

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