Pillar formation for heat dissipation and isolation in vertical field effect transistors
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United States of America Patent
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Aug 29, 2017
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N/A
app pub date -
Oct 11, 2016
filing date -
Oct 11, 2016
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Abstract
A method of fabricating a vertical field effect transistor includes forming fins from a portion of a substrate. At least a first fin of the fins is associated with a first device, at least a second fin of the fins is associated with a second device. The method includes forming alternating pillars of a first polymer and a second polymer on the substrate, removing the pillars of the second polymer except between two or more fins of a same device, and forming the substrate pillars below the pillars of the first polymer. The etching creates a deep trench between the first fin and the second fin. Removing the pillars of the first polymer and any remaining ones of the pillars of the second polymer is followed by performing an oxide fill to fill the deep trench and gaps between the pillars of the substrate with oxide.
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