Self aligned top extension formation for vertical transistors

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United States of America Patent

PATENT NO 9748382
SERIAL NO

15332181

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Abstract

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A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Gluschenkov, Oleg Tannersville, US 263 3542
Mehta, Sanjay C Niskayuna, US 106 776
Mochizuki, Shogo Clifton Park, US 296 1871
Reznicek, Alexander Troy, US 1406 11120

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