Memory controller load balancing with configurable striping domains

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United States of America Patent

PATENT NO 9753854
SERIAL NO

14747044

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Abstract

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Managing data in a computing system comprising a plurality of cores includes: assigning an address within a memory address space for access by one of a plurality of memory controllers coupled to different respective cores based on a designated portion of the address. The designated portion is selected to exclude one or more highest order bits and bits that correspond to a cache line associated with the memory address. In response to a memory access request at one of the cores to access data stored at the address, the system determines which of the plurality of memory controllers to which the memory access request is to be directed based on the designated portion of the address.

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Patent Owner(s)

  • MELLANOX TECHNOLOGIES LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bao, Liewei Westford, US 19 570

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