Timing adjustments across transparent latches to facilitate power reduction
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United States of America Patent
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Sep 5, 2017
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app pub date -
Nov 6, 2015
filing date -
Nov 6, 2015
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Abstract
A method of implementing timing adjustments across a transparent latch of an integrated circuit, a system, and a computer program product are described. The method includes obtaining initial input timing slack and input potential power savings at an input and an initial output timing slack and output potential power savings at an output of the transparent latch. The method also includes adjusting a cycle boundary of the transparent latch to obtain a new input timing slack at the input and a new output timing slack at the output of the transparent latch, wherein the new input timing slack is greater than the initial input timing slack based on the input potential power savings being greater than the output potential power savings and the new output timing slack is greater than the initial output timing slack based on the output potential power savings being greater than the input potential power savings.
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