Method for reduced source and drain contact to gate stack capacitance
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United States of America Patent
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Sep 5, 2017
Issued Date -
N/A
app pub date -
Dec 17, 2015
filing date -
Dec 17, 2015
priority date (Note) -
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Abstract
A structure and method for fabricating a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.
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