Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same
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United States of America Patent
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Sep 12, 2017
Issued Date -
N/A
app pub date -
Jun 27, 2016
filing date -
Jun 27, 2016
priority date (Note) -
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Abstract
One aspect of the present disclosure provides an interposer for a semiconductor package. The interposer includes a substrate portion and a wall portion disposed on the substrate portion. The substrate portion has a first side, a second side, and an electrical interconnect structure between the first side and the second side. The substrate portion is substantially free from conductive through vias, and the cost for fabricating through silicon vias (TSV) is very expensive; therefore, the fabrication cost of the interposer can be dramatically reduced. In addition, the wall portion is disposed on the first side and defining an aperture exposing a portion of the electrical interconnect structure. At least one semiconductor die can be bonded to the interposer and inside the aperture. Consequently, the height of the semiconductor package is lower than the design of disposing the semiconductor die on top of the interposer.
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