Access signal conditioning for memory cells in an array

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United States of America Patent

PATENT NO 9767899
SERIAL NO

15366293

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Abstract

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A memory is described having an array including two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power and a disturb isolator circuit operatively coupled to the MEs to compensate for disturbances of a magnitude of a signal associated with a selected two-terminal resistive memory element in the array.

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Patent Owner(s)

  • UNITY SEMICONDUCTOR CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chevallier, Christophe Palo Alto, US 141 2436
Siau, Chang Hua Saratoga, US 70 1564

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