Power semiconductor substrates with metal contact layer and method of manufacture thereof
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United States of America Patent
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Sep 19, 2017
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app pub date -
May 12, 2008
filing date -
May 12, 2007
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Abstract
A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer.
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