Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Sep 19, 2017
Issued Date -
N/A
app pub date -
Oct 27, 2014
filing date -
Oct 31, 2013
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully