Low power integrated clock gating cell with internal control signal
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United States of America Patent
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Sep 19, 2017
Issued Date -
N/A
app pub date -
Mar 23, 2016
filing date -
Jan 8, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
According to one general aspect, an apparatus may include a latch, and a control circuit. The latch may receive an input enable signal and generate a latched enable signal. The latch may also pass the input enable signal to the latched enable signal when the latch is transparent. The control circuit may be electrically coupled to the latch. The control circuit may receive as input an ungated clock signal, and generate a gated clock signal and a latch control signal. The latch control signal may be configured to make the latch transparent when the ungated clock signal is in a predefined state and when one of the input enable signal and the latched enable signal are in an enabled state. The control circuit may be configured to pass the ungated clock signal to the gated clock signal when the latched enable signal is in the enabled state.
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