Memory interface signal reduction

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United States of America Patent

PATENT NO 9772799
SERIAL NO

14981307

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Abstract

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In some embodiments a controller includes a memory activate pin, one or more combined memory command/address signal pins, and a selection circuit adapted to select in response to the memory activate pin as each of the one or more combined memory command/address signal pins either a memory command signal or a memory address signal. Other embodiments are described and claimed.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nale, Bill Livermore, US 73 842

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