Non-volatile semiconductor memory device and erase method thereof
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United States of America Patent
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Oct 3, 2017
Grant Date -
Feb 16, 2017
app pub date -
Aug 10, 2016
filing date -
Aug 12, 2015
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Abstract
Provided is an erase method for a non-volatile semiconductor memory device to compensate for the change in property of a memory cell, in proportion to the number of data rewrites to the memory cell. The erase method has an erase step to erase charges of a charge accumulation layer by applying an erase voltage to a channel region of a selected memory cell, and a soft-programming step to perform soft-programming to the charges in the accumulation layer by virtue of applying a soft-programming voltage which is smaller than a programming voltage to program the memory cell. The erase voltage is increased step by step when it is applied repeatedly. The soft-programming voltage is decreased step by step when it is applied repeatedly.
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