Simultaneous and selective wide gap partitioning of via structures using plating resist
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United States of America Patent
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Oct 3, 2017
Issued Date -
N/A
app pub date -
Mar 11, 2014
filing date -
Mar 15, 2013
priority date (Note) -
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Abstract
A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.
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