Regulator
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United States of America Patent
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Oct 10, 2017
Issued Date -
N/A
app pub date -
Nov 16, 2016
filing date -
Jan 8, 2016
priority date (Note) -
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status (Latency Note)
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Abstract
A regulator 100 is provided. The regulator 100 includes an output transistor M1 controlled by an output of an error amplifier circuit 104; a first MOS transistor M2 having a gate that is connected to a first terminal; a second MOS transistor M3, having a source that is connected to a second terminal 102, having a gate and a drain that are connected to a drain of the first MOS transistor M2; and a third MOS transistor M4, having a drain that is connected to a drain of the output transistor M1, having a gate that is connected to a gate of the second MOS transistor M3, and having a source that is connected to the second terminal 102. An output of the error amplifier circuit 104 is connected to a source of the first MOS transistor M2 via a signal processing circuit 110 or 210.
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