Methods and apparatus to eliminate partial-redundant vector loads

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United States of America Patent

PATENT NO 9785413
SERIAL NO

14741160

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Abstract

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Methods, apparatus, systems and articles of manufacture are disclosed to eliminate partial-redundant vector loads. An example apparatus includes a node group to associate a vector operation with a node group based on a load type of the vector operation. The example apparatus also includes a candidate identifier to identify a candidate in the node group, the candidate to include a subset of vector operations of the node group. The example apparatus also includes a code optimizer to determine replacement code based on a characteristic of the candidate, and to compare an estimated cost associated with executing the replacement code to a threshold cost relative to a cost of executing the candidate. The example apparatus also includes a code generator to generate machine code using the replacement code when the estimated cost of executing the replacement code satisfies the threshold cost.

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Patent Owner(s)

  • INTEL CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Borges, Leonardo Jose Houston, US 4 23
Kreitzer, David L Manassas, US 8 43
Krishnaiyer, Rakesh Milpitas, US 15 163
Preis, Sergey Novosibirsk, RU 4 78
Schuchman, Farhana Aleen Santa Clara, US 2 19
Thierry, Philippe Igny, FR 4 22
Zakharin, Vyacheslav Pavlovich Berdsk, RU 2 19

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