Low cost and mask reduction method for high voltage devices

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United States of America Patent

PATENT NO 9793153
APP PUB NO 20160254347A1
SERIAL NO

14633785

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Abstract

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Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

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Patent Owner(s)

  • ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lui, Sik Sunnyvale, US 84 1692
Tsuchiko, Hideaki San Jose, US 25 328

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