Reference-less clock and data recovery circuit

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9793902
SERIAL NO

15048040

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Embodiments herein describe a reference-less CDR circuit that receives electrical signals that may have been transmitted along either an electrical or optical interconnect which are then processed to identify the original data. To do so, the CDR circuit includes a frequency locking loop (FLL) and a phase locking loop (PLL) which generate control signals for a voltage controlled oscillator (VCO). In one embodiment, the FLL generates a coarse adjustment signal which the VCO uses to output a recovered clock that substantially matches the frequency of the received electrical signal. The PLL, on the other hand, generates a fine adjustment signal which the VCO uses to make small adjustments (e.g., half cycle phase shifts) to the recovered clock. The recovered clock outputted by the VCO is then fed back and used as an input in both the FLL and the PLL.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
CISCO TECHNOLOGY, INC.SAN JOSE, CA14590

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Dama, Bipin San Jose, US 21 128
Das, Bibhu Richardson, US 2 0
Lakshmikumar, Kadaba San Jose, US 6 19
Tse, Mark Y Basking Ridge, US 3 0

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