Range and process compensation for a digital phase locked loop (PLL) or frequency locked loop (FLL) circuit
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United States of America Patent
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Oct 17, 2017
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N/A
app pub date -
Aug 30, 2016
filing date -
Aug 30, 2016
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Abstract
A locked loop circuit includes a controlled oscillator generate an output signal having a frequency set by an analog control signal. The analog control signal is generated by a first digital-to-analog converter (DAC) in response to a digital control signal and a bias compensation current signal. The bias compensation current signal is generated by a second DAC in response to a compensation control signal and a bias reference current. A compensation circuit adjusts the compensation control signal during compensation mode in response to a comparison of a frequency of the output signal to a frequency of a reference signal so as to drive the frequency of the output signal toward matching a desired frequency. The bias compensation current signal associated with the frequency match condition during compensation mode is then used during locked loop mode.
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