Power switch with source-bias mode for on-chip powerdomain supply drooping

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United States of America Patent

PATENT NO 9798344
SERIAL NO

15236743

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Abstract

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This invention is an electronic circuit with a low power retention mode. A single integrated circuit includes a circuit module and a droop switch circuit supplied by a voltage regulator. In a normal mode a PMOS source-drain channel connects the voltage regulator power to the circuit module power input or isolates them dependent upon a power switch input. In a low power mode a second PMOS connected between the first PMOS gate and output diode connects the first PMOS. This supplied the circuit module from the voltage regulator power as reduced in voltage by a diode forward bias drop. This lower voltage should be sufficient for flip-flops in the circuit module to retain their state while not guaranteeing logic operation. There may be a plurality of chain connected droop switch each powering a corresponding circuit module.

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Patent Owner(s)

  • TEXAS INSTRUMENTS INCORPORATED

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Flores, Jose Luis Richardson, US 21 144
Gill, Michael Plano, US 20 231
Purushotaman, Soman Wayanad, IN 2 3
Stelmach, Shane Allen, US 3 8
Venkatasubramanian, Ramakrishnan Plano, US 45 229

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