Bus arbitration with routing and failover mechanism

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United States of America Patent

PATENT NO 9798688
SERIAL NO

14216627

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Abstract

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In one embodiment of the invention, a system architecture for bus masters and bus arbiters are provided to support routing and failover. The system comprises large pools of bus masters, a plurality of sets can be configured to control a plurality of slave devices wherein each set contains a collection of bus masters attached to central arbiter driving one of the system buses. Each set controls a group(s) of slave device that are primarily controlled by the bus master(s) within the set. Hence, a system can therefore include of a plurality of sets and can control a group of slave devices.

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Patent Owner(s)

  • BITMICRO NETWORKS, INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bruce, Ricardo H Fremont, US 29 1757
Espuerta, Jarmie Dela Cruz Bacolod, PH 3 1
Ponce, Cyrill Coronel Malabon, PH 4 3

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