Dram circuit, redundant refresh circuit and refresh method

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United States of America Patent

PATENT NO 9799391
SERIAL NO

15357420

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Abstract

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A DRAM circuit includes an array having a normal word line, a first redundant word line and a second redundant word line immediately adjacent to the first redundant word line. The second redundant word line is activated if the normal word line is assigned, by a memory controller external to the DRAM circuit, to be activated. A redundant refresh circuit is configured to determine that the first redundant word line is required to be refreshed in response to the second redundant word line being activated; and a row decoder is configured to, according to the determination of the redundant refresh circuit, refresh the first redundant word line.

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Patent Owner(s)

  • NANYA TECHNOLOGY CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Wei, Tzu Yin Hsinchu, TW 1 68

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