Memory circuit with leakage compensation
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United States of America Patent
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Oct 24, 2017
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N/A
app pub date -
Feb 23, 2016
filing date -
Feb 23, 2016
priority date (Note) -
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Abstract
A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.
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