Integrated circuit having a staggered fishbone power network
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United States of America Patent
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Oct 24, 2017
Grant Date -
Jul 6, 2017
app pub date -
Dec 30, 2015
filing date -
Dec 30, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
An integrated circuit includes: a first spine formed on a first conductive layer of the integrated circuit, the spine runs in a first direction; a first plurality of ribs formed on a second conductive layer of the integrated circuit, the first plurality of ribs run parallel to one another in a second direction that is orthogonal to the first direction and overlap respective portions of the first spine; a first plurality of interlayer vias formed between the first and second conductive layers, each of the plurality of interlayer vias electrically couple respective ones of the first plurality of ribs to the first spine at the respective portions of overlap; and a plurality of signal lines formed on the second conductive layer and running parallel to one another in the second direction.
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