Selecting master time of day for maximum redundancy

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United States of America Patent

PATENT NO 9804938
SERIAL NO

14930021

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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An approach is provided in which a system selects a first processor as a master Time of Day (TOD) processor in a first TOD topology. The system then assigns a second processor as an alternate master TOD processor to a second TOD topology based upon determining that the second processor is on a different node than the first processor. The system configures to the first TOD topology and, when the system detects a TOD failure requiring a topology switch, the system re-configures to the second TOD topology.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chowdhary, Manish Kumar Bangalore, IN 6 3
Kodihalli, Deepak Bangalore, IN 9 7

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